AMD Piledriver CPU with 10 Cores and Quad Channel Support
AMD Piledriver will be led to Mass Production
A few months ago we learnt that AMD is working on Piledriver, its new architecture that will replace the current Bulldozer modules. Piledriver modules will form the CPU part of AMD Trinity processor and Vishera processor. Vishera is the successor of (Zambezi) AMD FX CPUs, whereas Trinity APU is the successor of Llano APU with integrated HD 7000 series GPUs. Just 2 days back we were discussing about the leaked information on Phenom II X8 processors with doubled L1 and L2 cache memories of Bulldozer, now we have the details of PileDriver modules.
Software Optimization Guide revealed by AMD
A few days ago, AMD posted a new technical document, titled Software Optimization Guide for AMD Family 15h Processors. The guide has revealed some useful information about AMD Family 15h, i.e. Bulldozer. The document has clearly described the features of
- Current Bulldozer model 00h – 0fh (0xh)
- Future generations model 10h – 1fh (1xh) and 20h – 2fh (2xh)
We believe that microprocessors with 10h and higher model numbers will be based on Piledriver cores.
Features of AMD Piledriver CPU
| Feature | Model 0xh | Model 1xh | Model 2xh |
|---|---|---|---|
| Core | Zambezi / Interlagos / Valencia | Trinity | Vishera / Terramar / Sepang |
| L3 cache | Yes | None | Yes |
| 16-bit floating point type | No | Yes | Yes |
| F16C (VCVTPH2PS and VCVTPS2PH) | No | Yes | Yes |
| FMA3 | No | Yes | Yes |
| BMI instructions | No | Yes | Yes |
| TBM instructions | No | Yes | Yes |
| Size of L1 data TLB | 32 entries | 64 entries | 64 entries |
| Max number of cores | 8 | 4 | 10 |
| DDR3 channels | 2 | 2 | 4 |
| Depth of FPU load queue | 40 | 44 | 44 |
| HyperTransport Assist feature | Yes | No | Yes |
| IOMMU | v1 | v2 | Not Known |
The features, applicable to both 1xh and 2xh CPUs are
- Support for 16-bit floating point numbers
- Support for addition of VCVTPH2PS and VCVTPS2PH instructions to convert “to and from” new 16-bit floating-point type.
- Support for Bit Manipulation Instructions (BMI)
- Support for Trailing Bit Manipulation instructions
- Increased depth of FP load queue
- Larger size of level 1 data TLB
- Reduces instruction latency
Characteristics of 1xh model CPU
The characteristics of 1xh model microprocessor is expected to match upcoming Trinity core
- It will have 2 modules or 4 cores
- It will have no L3 cache like Athlon Processors
- It will have enhanced IOMMU, or IOMMU v2,
- It will have improved access of I/O devices to system memory
- It will support interrupt remapping and filtering
Characteristics of 2xh model CPU
- It will have up to 5 modules, or up to 10 cores
- It will support quad-channel DDR3 memory
